Radix-4 알고리즘을 이용한 다치 승산기 설계

Design of Multi-Valued Multiplier using Radix-4 Algorithm

This paper presents that multiple-valued full adder circuit can be implemented using The fundamental circuit of current mode CMOS techniques. It can be reducing the transistor, wires count to half compared to that of a binary implementation. For adder processing without carry propagation in SOFA(Signed digits full adder), We used digit set ｛0,1,2｝ in the radix-2 full adder, and used digit set｛0,I,2,3｝ in the radix-4 full adder. We have H-spice simulation with 0.35um with SDFA and desiged with lC station of the MENTOR corporation. Finally, Multiple-valued processor was presented to be compatible on binary system. For compatibility between MVL and binary, we use binary-four valued encoder, four valued-decoder and current mode CMOS circuit.