학술저널
3-Lavel PLA實現 및 EXCLUSIVE - OR셀 어레이 LAYOUT 硏究
“The Reseach On 3-Level PLA Implementation And Layout of Exclusive-OR Cell Array”
- 호서대학교 사회과학연구소
- 사회과학연구
- 제4집 제1호
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1985.12419 - 431 (13 pages)
- 6
In this paper deal with the theoretical method of 3-level PLA and design of exclusive-OR array cell for 3-level PLA. Most PLA have constraints on minimal chip area and minimal input lines, thus the reduction of the number of product term in a sum of products expression is important in conventional random logic circuits. Also, this paper deals with lay out of Exclusive-ORArray using CHISEL language.
ABSTRACT
Ⅰ. 序論
Ⅱ. 3LEVEL PLA 實現
Ⅲ. Exclusive-OR Array Cell 設計 및 Layout
Ⅳ. 結論
參考文獻
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