논리희로의 네트리스트를 입력으로 하는 VHDL 생성기 개발

Development of a VHDL Generator Which Inputs Logic Netlists

This study concerns about a structural description of VHDL which is a standard hardware description language for the VLSI. We have developed a generator which inputs logic netlists of digital circuits and produces VHDL descriptions which have structural architectures according to the netlists. The purpose of this study is to translate designs which have been designed already by traditional methods such as schematic editors, into VHDL in structural description, so that the old designs could have a technology independent and standard forms. The significance of the study is first in reducing the effort to construct VHDL libraries for basic modules, second in upgrading the old design with new methodology, and third in applying new low level synthesis tools in the future to old designs. As an input logic netlist, we have chosen MIF(MyCAD Intermediate Form) which is the logic netlist of MyCAD from Seodu Logic. After parsing the netlist, the entity declaration and architectural bodies for the structure of the entity are produced following the connectivity of the components in the netlist. The developed generator has produced good VHDL statements of entities and architectures for the input netlist.