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학술저널

VITAL을 이용한 VHDL TTL 라이브러리 연구

A Study on VHDL TTL Library following VITAL

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A TTL library is described in VHDL following VITAL which is a new standard timing constraints on VHDL. Using VITAL packages, timing delay was obtained as near practical value. 39 cells in TTL ALS library have been designed and simulated in VHDL. With the aid of the VHDL TTL library, traditional design which is using TTL library can be translated in VHDL. Example TTL circuit designs are shown with acceptable results comparing both using VITAL and not using VITAL packages.

ABSTRACT

1. 서론

2. VHDL과 VITAL

3. VHDL TTL 라이브러리

4. 응용실험

5. 결론

참고문헌

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