PLD 소자를 이용한 programmable delay 회로 설계

The circuit design for programmable delay using PLD device

In the signal progresses, tim e delay can happen, and bring the operation error by the delay. D ig ital signal sets the tim in g to clock signal th a t get into ordinary standard. T he delay of signal can bring the operational fatal error by th at h ig h speed d ig ita l system achieves CPU , R A M , R O M , F P G A and interface IC s and organic action fast usually, c^kew can happen by such delayed signals and the serious problem in signal progresses can be happened on the sem iconductor device testing or other dig ital circuit operating by the skew. T o solve these problem s, the device th at m ake the exact delay m ust be used. T o m ake a exact delay can be done by using delay com ponents. How ever, m any delay com ponents m ust be used in the circuit design for com plex delay structure. In this paper, w e propose the program m able delay m ethod/circuit using P L D device. T he proposed m ethod has m any advantages, because th at uses interior gates of P L D device from Ins to several ns delay the circuit designer can do program m ing voluntarily, and prove precision.