STM-1 통신용 CMOS 트랜시버의 설계

Design or a CMOS Transceiver for STM-1 Communication

A CMOS transceiver ASIC for the 155.52 Mbps STM-1 digital communication system etc., was designed. It transmits 155.52 Mbps serial data transformed from 19.44 Mbps parallel data. 155.52 MHz clock for synchronization of data is generated using reference 19.44 MHz clock by an analog PLL while parallel to serial datac onversion is done by a digital circuit. The transceiver receives 155.52 Mbps serial data and transforms to 19.44 Mbps parallel data. 155.52 MHz clock for synchronization of data is recovered using 155.52 Mbps input data by an analog PLL while serial to parallel data conversion is done by a digital circuit. Circuit simulations confirm that PLL locking and data conversion are accomplished successfully. The area of the designed ASIC chip is 3.0 X 3.8 mm2 using 0.6 fim process and the estimated power consumption of the chip are less than 300 mW with a single 5 V supply, respectively.