A High Performance Parallel Architecture for Matrix Operations

In the digital signal processing (DSP) area, matrix operations have been necessary parts of many high-resolution algorithms. However, these operations require tremendous computations and this makes it difficult to implement them in real-time. Also, the size of the matrix to be solved may vary with time for many applications. We present a high performance parallel architecture which can handle these problems. The architecture is flexible in the sense that the same number of processing elements can be used to solve a complex set of problems with different sizes for the input matrix. It achieves high efficiency and high throughput by using asynchronous data communication and parallel block processing. We have simulated the architecture with a programmable simulator using the timing characteristics of the TMS320C40 digital signal pix>cessor. The simulation results consistently show that the parallel architecture can provide high performance, high efficiency, and almost linear speedup for many applications.