적응루프필터를 사용한 낮은 지터특성의 전하펌프PLL 클록발생기

A Low-Jitter CPPLL Clock Generator using Adaptive Loop Filter

This paper describes that the timing jitter is affected by changes of the scale factor N of a CPPLL(Charge-Pump Phase-Locked Loops) clock generator. The noise due to VCO(Voltage Controled Oscillator) is considered mainly, then the closed-form equations are derived from CPPLL output timing jitter related to parameters of a second-order CPPLL that simplified a third-order CPPLL. Verifying the performance, the variation of damping factor ？？ and natural frequency ？？ when the scale factor N is changed is estimated into Matlab analysis, the CPPLL clock generator that has digitally tunable bandwidth is integrated with CMOS technology. The proposed architecture shows that it maintains the output timing jitter around the 1% per half-period although the scale factor N is changed. The output timing jitter of the CPPLL clock generator using the adaptive loop filter is improved to the maximum 47% compared with a typical CPPLL clock generator when the scale factor N is changed.