전류 셀 매트릭스구조에서 전류구동 저 전력 10-비트 CMOS D/A변환기의 설계

A Design of 10-Bit CMOS Digital to Analog Converter in Low-Power Current Driving of Current Cell Matrix Architecture

In this paper, a highly linear and low glitch 10-bit CMOS current mode digital-to-analog converter(DAC) by low-power current driving is proposed. The architecture of the DAC is based on a current steering 6+4 segmented type and new switching scheme for the current cell matrix, which reduced npn-linearity errorand graded error. In order to achieve a high performance DAC, novel current cell with a low spurious deglitching circuit and a new inverse thermometer decoder are proposed. The prototype DAC was implemented in a 0.35？？ n-well CMOS technology. Experimental result show that SFDR is 60dB when sampling frequency is 32MHz and DAC output frequency is 7.92MHz. The DAC dissipates 46mW at a 3.3 Volt single power supply and occupies a chip area of 1350um × 750um.