듀얼-타입 전류 셀 매트릭스구조에서 CMOS D/A변환기의 설계

A Design of CMOS Digital to Analog Converter in Dual-Type Current Cell Matrix Architecture

This paper describes a 3.3(V) 8 bit CMOS digital to analog converter (DAC) in dual-type current cell matrix architecture which consists of a 4 MSB and a 4 LSB current matrix stage. The symmetric dual-type current cell matrix architecture allows the designed DAC to reduce not only a complexity of decoding logics, but also a number of wide swing cascade current mirrors. The designed DAC with an active chip area of 0.8(mm2)is fabricated by a 0.8(？？) CMOS n-well standard analog process. The experimental data shows that the rise/fall time, the settling time, and INL/DNL are 6(ns), 15(ns) and a less than ±0.8 ±？？0.75 LSB, respectively. The designed DAC is fully operational for the power supply down to 2.2(V), such that the DAC is suitable for a low voltage and a low power system application. The power dissipation of the DAC with a single power supply of 3.3(V) is measured to be 34.5(㎽).