연산증폭기의 슬루율 개선을 위한 병렬 전류감산기 설계

A Design of Improvements Slew-Rate Operating Amplifier Parallel Current Subtracter

This paper presents the design of Improvements slew-rate operating amplifier parallel current subtracter. In the circuit designed for slew-rate programmability is based upon a newly proposed concept, that is a switched parallel current subtraction circuit with adaptive biasing technique. If the programmable slew rate amplifier is employed into mixed signal system, it can furnish the convenience timing control and optimized power dissipation. Simulated data showed the slew rate ranging from 4.17V/db to 20V/db, power dissipation ranging from 7.67mW to 3.87mW and the other circuit performance parameters were proven to be comparable with those of a conventional operational amplifier.