새로운 지수연산 블록 구조를 갖는 고속 저전력 베다 곱셈기의 설계

A Vedic Multiplier with A Novel Architecture of Exponent Block for High-Speed and Low-Power

Vedic Mathematics is based on 16 formulas with the purpose of simplification of lengthy and complex mathematics. NND(Nikhilam Navatashcaramam Dashatah) sutra is most efficient algorithm, giving minimum delay for multiplication of all types numbers. In this paper modified vedic multiply algorithm has been devised at architecture level to improve the speed and power of the multiplier. The main idea of the improvement is based on using priority encoder in residue exponent determinant unit. The proposed multiplier results in 45% of speed-up and 42% of reduction of power consumption. This multiplier is composed of Xilinx FPGA and designed RTL(Register Transfer Level) using Xilinx ISE software.