CMOS 공정에서 안테나 효과를 최소로 하기위한 레이아웃 방법에 관한 고찰

The Study of Physical Layout Methods for Reducing Antenna Effect in CMOS Process

The antenna effect is that electromagnetic waves induce the strong accumulated charges in the interconnected metals connected to poly silicon gate of MOSFET during plasma processing of wafer and the accumulated charges break down gate oxide. A techniques can be utilized to minimize the antenna effect is the predicting of the occurrences of antennas by using layout and design verification software programs. Then by adjusting the physical layout of the inter-connects, the antenna effect can be reduced to an acceptable level. In addition, processing steps utilizing plasma can be optimized to reduce the build-up of charges on any antennas that do exist on devices. In this paper, several techniques of physical layout is studied and proposed new methode of physical layout to reduce antenna effect.