단일 패스 연결 요소 레이블링을 위한 SoC 기반 Simulink 모델링에 관한 연구

Simulink Modeling Based on SoC for Single-Pass Connected Component Labeling

In this study, a single-pass connected-component labeling algorithm based on Bailey and Johnston was designed using Simulink modeling to resolve processing time delays in typical double scan labeling algorithms. The algorithms were used to compare the processing time of the logic-based Bailey and Johnston algorithm with a typical double pass algorithm-based Intel SoC FPGA. From the experimental results, a single sample image of 1280 × 720 high-definition resolution showed that the typical double-pass algorithm and the Bailey and Johnston algorithm had processing times of 7770.76 and 22.975 ms, respectively.