STI 채널 모서리에서 발생하는 MOSFET의 험프 특성

The MOSFET Hump Characteristics Occurring at STI Channel Edge

An STI(Shallow Trench Isolation) by using a CMP(Chemical Mechanical Polishing) process has been one of the key issues in the device isolation[1]. In this paper we fabricated N, P-MOSFET to analyze hump characteristics in various rounding oxidation thickness(ex : Skip, 500, 800, 1000Å). As a result we found that hump occurred at STI channel edge region by field oxide recess, and boron segregation(early turn on due to boron segregation at channel edge). Therefore we improved that hump occurrence by increased oxidation thickness, and control field oxide recess(≤20nm), wet oxidation etch time(19HF, 30sec), STI nitride wet cleaning time(99HF, 60sec+P 90min) and gate pre-oxidation cleaning time (U10min+19HF, 60sec) to prevent hump occurring at STI channel edge.