KCI등재
학술저널
A Study of Wire Sweep During Encapsulation of Semiconductor Chips
A Study of Wire Sweep During Encapsulation of Semiconductor Chips
- 한국마이크로전자및패키징학회
- 마이크로전자 및 패키징학회지
- 제7권 제4호
- : KCI등재후보
- 2000.12
- 17 - 22 (6 pages)
In this paper, methods to analyze wire sweep during the semiconductor chip encapsulation have been studied. The wire sweep analysis is used to analyze the deformation of bonding wires that connect the chip to the leadframe during encapsulation. The analysis is done using either analytical solutions or numerical simulation. The analytical solution is used for rough but fast calculation of wire sweep. The results from the numerical simulation are closest to the experimental results.
1. Introduction
2. Wire Sweep Analysis
3. Conclusion
References