Preparation of Field Effect Transistor with (Bi,La)Ti₃O₁₂ Gate Film on Y₂O₃/Si Substrate

Preparation of Field Effect Transistor with (Bi,La)Ti₃O₁₂ Gate Film on Y₂O₃/Si Substrate

The field effect transistors (FETs) were fabricated ell Y₂O₃/Si(100) substrates by the conventional memory processes and sol-gel process using (Bi,La)Ti₃O₁₂(BLT) ferroelectric gate materials. The remnant polarization (2Pr = Pr⁺-Pr⁻) int Pt/BLT/Pt/Si capacitors increased from 22 μC/cm² to 30μC/ cm² at 5V as the annealing temperature increased from 700℃ to 750℃. There was no drastic degradation in the polarization values after applying the retention read pulse for 10⁵‧⁵ seconds. The capacitance-voltage data of Pt/BLT/Y₂O₃/Si capacitors at 5V input voltage showed that the memory window voltage decreased from 1.4V to 0.6V as the annealing temperature increased from 700℃ to 750℃. The leakage current of the Pt/BLT/Y₂O₃/Si capacitors annealed at 750℃ was about 510⁻⁸A/cm² at 5V. From the drain currents versus gate voltages (V_G) for Pt/BLT/Y₂O₃/Si(100) FET devices, the memory window voltages increased from 0.3V to 0.8V with increasing tile V{_G} from 3V to 5V.