국가지식-학술정보
플립칩용 웨이퍼레벨 Fine Pitch 솔더범프 형성
Fabrication of Wafer Level Fine Pitch Solder Bump for Flip Chip Application
- 한국전기전자재료학회
- Journal of the Korean Institute of Electrical and Electronic Material Engineers
- Vol.14 No.11
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2001.01874 - 878 (5 pages)
- 0
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Solder bump was electroplated on wafer for flip chip application. The process is as follows. Ti/Cu were sputtered and thick PR was formed by several coating PR layer. Fine pitch vias were opened using via mask and then Cu stud and solder bump were electroplated. Finally solder bump was formed by reflow process. In this paper, we opened 40㎛ vias on 57㎛ thick PR layer and electroplated solder bump with 70㎛ height and 40㎛ diameter. After reflow process, we could form solder bump with 53㎛ height and 43㎛ diameter. In plating process, we improved the plating uniformity within 3% by using ring contact instead of conventional multi-point contact.
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