Multi-channel 5Gb/s/ch SERDES with Emphasis on Integrated Novel Clocking Strategies

Multi-channel 5Gb/s/ch SERDES with Emphasis on Integrated Novel Clocking Strategies

Two novel clocking strategies for a highspeedmulti-channel serializer-deserializer (SERDES)are proposed in this paper. Both of the clockingstrategies are based on groups, which facilitateflexibility and expansibility of the SERDES. Oneclocking strategy is applicable to moderate parallelI/O cases, such as high density, short distance,consistent media, high temperature variation, whichis used for the serializer array. Each group within thestrategy consists of a full-rate phase-locked loop(PLL), a full-rate delay-locked loop (DLL), and twofixed phase alignment (FPA) techniques. The other isapplicable to more awful I/O cases such as higherspeed, longer distance, inconsistent media, seriouscrosstalk, which is used for the deserializer array. Each group within the strategy is composed of a PLLand two DLLs. Moreover, a half-rate version ischosen to realize the desired function of 1:2deserializer. Based on the proposed clocking strategies,two representative ICs for each group of SERDES aredesigned and fabricated in a standard 0.18 μm CMOStechnology. Measurement results indicate that the twoSERDES ICs can work properly accompanied withtheir corresponding clocking strategies.

Two novel clocking strategies for a highspeedmulti-channel serializer-deserializer (SERDES)are proposed in this paper. Both of the clockingstrategies are based on groups, which facilitateflexibility and expansibility of the SERDES. Oneclocking strategy is applicable to moderate parallelI/O cases, such as high density, short distance,consistent media, high temperature variation, whichis used for the serializer array. Each group within thestrategy consists of a full-rate phase-locked loop(PLL), a full-rate delay-locked loop (DLL), and twofixed phase alignment (FPA) techniques. The other isapplicable to more awful I/O cases such as higherspeed, longer distance, inconsistent media, seriouscrosstalk, which is used for the deserializer array. Each group within the strategy is composed of a PLLand two DLLs. Moreover, a half-rate version ischosen to realize the desired function of 1:2deserializer. Based on the proposed clocking strategies,two representative ICs for each group of SERDES aredesigned and fabricated in a standard 0.18 μm CMOStechnology. Measurement results indicate that the twoSERDES ICs can work properly accompanied withtheir corresponding clocking strategies.