A Study of the CMP Effect on the Quality of Thin Silicon Films Crystallized by Using the μ-Czochralski Process

A Study of the CMP Effect on the Quality of Thin Silicon Films Crystallized by Using the μ-Czochralski Process

In this paper, the eect of chemical mechanical polishing on the μ-Czochralski process for amorphous silicon crystallization is reported. Amorphous silicon is deposited on both planarized and non-planarized surfaces in a low pressure chemical vapor deposition (LPCVD) system at 545 ℃ and is crystallized using a μ-Czochralski process. Large and regular single silicon grains are obtained on both planarized and non-planarized surfaces at high laser energies. However, at low laser energies, non-planarized surfaces deform the grains. This technique is used to stack silicon layers to realize three-dimensional integrated circuits using thin-film transistors at low temperatures. For 3D-IC advantages, planarized surfaces are needed and chemical mechanical polishing (CMP) has a key role in this process. Thin-film transistors were fabricated on planarized surface and showed high mobilities for nMOS and pMOS transistors of more than 450 cm<SUP>2</SUP>/Vs and 250 cm<SUP>2</SUP>/Vs, respectively.

In this paper, the eect of chemical mechanical polishing on the μ-Czochralski process for amorphous silicon crystallization is reported. Amorphous silicon is deposited on both planarized and non-planarized surfaces in a low pressure chemical vapor deposition (LPCVD) system at 545 ℃ and is crystallized using a μ-Czochralski process. Large and regular single silicon grains are obtained on both planarized and non-planarized surfaces at high laser energies. However, at low laser energies, non-planarized surfaces deform the grains. This technique is used to stack silicon layers to realize three-dimensional integrated circuits using thin-film transistors at low temperatures. For 3D-IC advantages, planarized surfaces are needed and chemical mechanical polishing (CMP) has a key role in this process. Thin-film transistors were fabricated on planarized surface and showed high mobilities for nMOS and pMOS transistors of more than 450 cm<SUP>2</SUP>/Vs and 250 cm<SUP>2</SUP>/Vs, respectively.